Keystone Semiconductor, Inc.

Welcome to the home of Positive Logic, ALL® and FLL!

The MOSFET is a simple switch that requires little power to operate; it is easy to make and it is an ideal switch because there is no direct interaction between the input signal and the output signal. The CMOS technology using MOSFET is a perfect technology that has become the main driving force for electronic products since 1970s.

Depending upon the default state of the MOSFET, there are two ways to implement the MOSFET by either using the enhancement mode or depletion mode operation. The transfer characteristics of the MOSFET are shown in above. For the P type enhancement MOSFET, the transistor is OFF when the gate-to-source junction is not energized and it becomes ON when the gate-to-source junction is energized with a negative voltage. The behavior of the N type depletion MOSFET is just the opposite to P type enhancement MOSFET that the transistor is ON when the gate-to-source junction is not energized and it becomes OFF when the gate-to-source junction is energized with a negative voltage. Consequently, the depletion MOSFET can produce logic circuits with polarity opposite to the enhancement MOSFET. The following logic circuits illustrate the difference between the two types of MOSFET.


Non-Inverting Buffer		Inverter

The benefit of positive logic operations is evident since a memory cell can be built from only one stage. This is a drastic improvement over existing negative logic technology that requires twice the amount of hardware for a memory cell.

For all the existing logic circuits using negative logic technology, we can replace the P type enhancement MOSFET with N type depletion MOSFET and N type enhancement MOSFET with P type depletion MOSFET to become new logic circuits that execute the same logic operations but producing results with opposite polarity.

The other benefit of positive logic is for ESD protection. Since the depletion MOSFET is ON by default, it can provide a short-circuit connection for the gate of input transistor to the power supply and ground when the transistor is not powered up. Consequently, the input impedance of the MOSFET can become too low to produce harmful ESD voltage to damage the gate of input transistor when the transistor is not powered up. The ESD protection circuit using depletion MOSFET is the only ESD technology that prevents the generation of harmful voltage spike on the gate of input transistor. The ESD protection with depletion MOSFET can be illustrated as follows. As soon as the transistors are powered up, the protection transistors will become pinched-off immediately so that they are transparent to the circuit it is protecting.

The ESD events will still produce a voltage spike to the circuits protected with depletion MOSFET; fortunately, the voltage spike now occurs on the robust power supply line or ground instead of the delicate gate structure of input transistor so that the circuits can survive ESD events easily.

ESD Protection

The complete patent application for the applications of depletion type MOSFET can be downloaded from the WIPO’s website through the following link. http://www.wipo.int/pctdb/en/wo.jsp?IA=WO2008092004

Evolution

The PFD which is made of two flip-flops and an AND gate as shown in the following figure was invented about 50 ago and it is one of the fundamental technologies of digital design. The PFD is simple and has been used for so long and yet, its characteristics have not been totally understood until today so that the only technology ever evolved from PFD is the digital PLL. However, once we fully understand the nature of PFD, we can develop many useful technologies which were impossible to do before as shown above from the same PFD. One example is the FLL technology; no one today can even build a FLL that produce a signal without frequency error quickly. The new FLL technology developed from PFD can finally do so easily just like the current PLL.

The PFD is simply a device to detect the arrival sequence between two signals without metastability problem. When the early signal arrives, either the UP or DOWN output will become true first; when the late signal finally arrives, both UP and DOWN will become true for a brief moment before being reset. Consequently, it can tell us which signal arrives first and which signal arrives last and these two things are the only things that the PFD does. From determining which signal arrives first, we can develop the arrival technology and from determining which signal arrives last, we can develop the frequency technology.

In the past, the UP and DOWN output of the PFD are used to enable a sourcing and sinking charge pump to produce an error output to correct the VCO. Since both the UP and DOWN will be enabled at the same time during the reset period of the flip-flop and since the amount of output current from two charge pumps will never be equal due to the intrinsic noise, the PFD produces an inevitable glitch so that the two signals could never arrive at the same time; whenever the two signals arrive at the same time, the glitch will push the two signals apart and it is the infamous dead-zone jitter problem. Currently, the only solution for this problem is to enlarge the glitch and to produce a constant phase error output to cancel out the glitch. Although it can reduce the impact of glitch, it is a flawed solution since the dead-zone is still an unstable singularity. The correct solution to use the PFD is to make it into an arrival detection circuit as shown below to produce the UP and DOWN output to drive the charge pumps so that the charge pumps will never be turned on at the same time regardless of how small the arrival-time difference is.

Since the late arrival signal produces the reset signal to clear both flip-flop, the reset signal tells us which signal is the late arrival signal. We can find out which signal is the faster signal in frequency by comparing the arrival of three copies of feedback signal with orthogonal phase offset with the same arrival of reference input signal with three PFDs.

Timing

If the reference signal is faster in frequency, the slower feedback signal will be the late signal to produce the reset signal most of the time. Since the three copies of feedback signal will arrive at different time, there will be three reset signals generated in an arrival comparison cycle. If the reference signal is slower in frequency, it will produce the reset signal most of the time. Since all the reference signals are the same signal, there will be only one reset signal generated in an arrival comparison cycle. Consequently, we can find out which signal is the faster signal precisely without error by counting how many reset signal is generated in an arrival comparison cycle.

Both the arrival detector and frequency detection are precise and error-free so that there is no dead zone jitter glitch regardless of how small the arrival-time difference is. Both technologies open a new frontier and produce many new useful circuits. The patent applications for these new technologies can be downloaded from the WIPO website as follows.